1. Field of the Invention
The invention relates to the field of semiconductor devices and, more particularly, materials and methods for interconnecting dual damascene copper wiring pathways with porous intermetal dielectrics.
2. Description of the Related Art
Semiconductor devices are made from multi-layer structures that are fabricated on semiconductor wafers. Dielectric materials are used to separate metallization interconnect lines. Three general techniques for fabricating metallization interconnect lines and conductive vias include: (i) a via first fabrication; (ii) self-aligned fabrication; and (iii) trench first fabrication. Damascene processing involves forming trenches in the pattern of the desired lines, overfilling the trenches with a metal or other conductive material, and then polishing the excess metal back to the insulating layer. Wires are thus left within the trenches, and may be isolated from or connected with one another in a desired connective pattern. The polishing process advantageously avoids the more difficult photolithographic mask and etching processes of conventional metal line definition. Typically, the interconnect metallization is a copper (Cu) material, and the conductive vias are also integrally formed of Cu.
FIGS. 1A through 1H are cross-sectional views illustrating various stages of a via-first dual damascene fabrication process. FIG. 1A shows a an interlayer dielectric stack deposition construct 100 where a first dielectric layer 102 has been etched to form a trench 104. that is filled with a copper line 106. A layer of etch-stop material 108 has been deposited atop the first dielectric layer 102 and the copper line 106. An interlayer dielectric material 110 covers the etch-stop material 108. By way of example, the first dielectric layer 102 and the interlayer dielectric material 108 may be fluorinated silicate glass (FSG) or carbon doped oxide (CDO). The copper line 106 is part of a horizontally extending metal line that operably connects with one or more integrated circuit functional elements, such as transistors (not shown). The etch stop material 108 may be a selective etch stop that additionally functions as a barrier material, such as silicon nitride (SiN) or silicon carbide (SiC).
The interlayer dielectric material 108 eventually is used to separate respective metallization layers, for example, to separate metal deposited at the level of copper line 106 from future materials to be deposited atop surface 112. In this context, it may be necessary or desirable to form a wiring interconnect extending from surface 112 to copper line 106. FIG. 1B illustrates a via 114 that has been etched for this purpose by the masked action (mask is not shown) of a first high power plasma P1 through the interlayer dielectric material 110 down to the etch stop material 108. FIG. 1C shows the results of a second etching step by the action of a second high power plasma P2, which forms a trench 116 in the interlayer dielectric material 110 (photoresist is not shown in the cross section). FIG. 1D illustrates the results of a third etching step by the action of a third high power plasma P3, which removes the etch-stop material 108 in region 116 at the bottom of via 114.
It is common practice to line contact vias and trenches with a conductive diffusion barrier, for example, barrier 120 as shown in FIG. 1E. The barrier 120 may, for example, be Ta, TaN, TaN/Ta deposited by physical vapor deposition (PVD), alternating layer deposition (ALD) or chemical vapor deposition (CVD) processes. The formation of barrier 120 is followed by the application of a copper seed layer 122, for example, by a PVD process, as shown in FIG. 1F. Copper seed layer 122 is expanded by electrodeposition of copper mass 124, as shown in FIG. 1G. The copper mass 124 is polished, for example, by chemical mechanical polishing (CMP) to leave an exposed conductive surface 126. The numeral 128 generally designates a completed interconnect level formed as described above.
Barrier 120 is intended to prevent diffusion and drift of copper atoms and ions, respectively, from copper mass 124 into interlayer dielectric material 110, and to prevent diffusion of the interlayer dielectric material 110 into copper mass 124. This type of diffusion, if it occurs, may result in line-to-line leakage or to electrical break-down of the interlayer dielectric material 110. One pathway towards faster semiconductor devices involves the use of low-k dielectrics. Conventional dense silicon dioxide (oxide) has a dielectric or permittivity constant “k” of about 4, and low k dielectrics may be defined as those having k values less than that of dense oxide. Reducing k-values below about 2.5 to 3 is achieved by introducing porosity to lower the material density. By way of example, leading precursors used in forming low k dielectrics include the SiLK product from Dow Chemical and the methyl silsesquioxane-based LKD-5109 product from JSR Micro of Sunnyvale, Calif. The resulting low k films have reduced structural integrity resulting, in part, from the increased porosity. The porosity may, for example, range as high as 50% to 90% when using mesostructured liquid precursors to make these materials. The higher porosity films may not have sufficient structural integrity for use in semiconductor devices.
A variety of materials and techniques are being developed for producing low k films in integrated circuits. Deposition methods currently include spin-on deposition, CVD, plasma enhanced CVD (PECVD) and high density plasma (HDP) CVD, depending upon the characteristics desired. Some of the methods and films have been described by Laura Peters, “Pursuing the Perfect Low-k Dielectric” Semiconductor International, Vol. 21, No. 10 (September 1998), and the references cited therein. Some films have a k value from 3 to 3.5 such as hydrogen silsesquioxane (HSQ) and fluorinated oxides. Organic polymers, such as benzoncyclobutene (BCB) and polyarylene ethers (PAE), exhibit even lower k values between the 2.5 and 3 range. Other work with polytetrafluoroethylene (PTFE) using spin-on techniques has achieved intrinsic k values of about 1.9.
Integrating these new materials with existing technologies, however, introduces new challenges. Among other requirements, low k films must exhibit high chemical, thermal and mechanical stability in the face of disparate adjacent materials and exposure to a variety of processing environments. ILD materials should be compatible with etching, deposition, cleaning and polishing processes in order to integrate reliably with a manufacturing process. Integration of new materials and processes into established process flows is rarely a straightforward matter, as evidenced by past complications whenever new materials are introduced.
The porous nature of low k materials is problematic in advanced miniaturization. For integration reasons, pore size needs to be significantly smaller than the smallest printed feature, in order to minimize feature to feature variation. Despite the small pore dimensions (typically, <20A) subsequent layers deposited on these porous materials tend to enter the pores. In particular, deposition of the barrier layers by ALD or CVD results in permeation of the barrier layer precursors into the pores. This leads to degradation of the ILD properties and potentially to device breakdown (shorts).
It is not practical to address the permeation problems by PVD processes, e.g., sputtering as opposed to MLx vapor or liquid, in dual damascene processes where high aspect ratio features must be coated with barrier material. As used herein, the term “aspect ratio” means a ratio of depth or width to thickness. A trench 116, as shown in FIG. 1D, is generally regarded as one type of feature potentially having a high aspect ratio. As is illustrated in FIG. 2A, numerous irregularities form in barrier materials deposited by PVD onto high aspect ratio features having nanoscale dimensions. Surfaces 200, 202, 204 present themselves in a right-normal orientation to a depositional path 206 from the PVD source (PVDs) and, consequently, obtain relatively thicker deposits forming barrier 120 at these surfaces. Corner overhangs 208, 210 tend to build up at surface transitions, for example from vertical wall 212 to horizontal wall 214. These overhangs 208, 210, together with the increased likelihood that downwardly descending PVD materials on path 206 will contact the right-normal surfaces 200, 202, 204, produce a downward thinning of barrier 120 along vertical walls 212, 216. The material deposited on walls 212, 216 is also relatively rough in surface texture. Additionally, the thickness of barrier 120 at the surface 204 of via 114 is less than that deposited on surfaces 200, 202, owing to the depth of via 114. In like manner, the thickness of barrier 120 deposited on surface 218 may be thinner than that of barrier 120 on surfaces 200, 202. In summary, the effect of these variations is to require that excessive material must be deposited to form barrier 120 on some surfaces, in order to meet minimum thickness requirements on other surfaces. In some designs of particularly high aspect ratio, it may not even be possible to obtain minimum thicknesses by PVD on some surfaces, due to the volume occupied by material deposited on other surfaces, for example, if the corner overhangs 208, 210 accumulate sufficiently to restrict PVD access into trench 116.
FIG. 2B provides a comparison showing the advantages of CVD or ALD deposition processes using metal (M) organic ligand (L) MLx vapor to deposit barrier 120. Barrier 120 is substantially uniform on all surfaces of via 114 and trench 116, and the irregularities shown in FIG. 2A are absent.
FIG. 3 illustrates a permeation problem arising in context of forming the barrier 120 using MLx vapor, as depicted in FIG. 2B. The problem may be particularly acute when the interlayer dielectric material 110 is a porous or low k material. FIG. 3A shows a metalorganic precursor (MLx) being applied in vapor form to deposit barrier coating 302 as shown on surfaces that define via 114 and trench 116, where barrier coating 302 is a precursor to barrier 120. Because of the porous nature of the interlayer dielectric material 110, MLx penetrates into the trench and via sidewalls to forming a diffusion layer or zone 304. FIG. 3B is a square balloon diagram of region 306 from FIG. 3A illustrating additional detail with respect to the diffusion layer 304. The boundary of trench 114 is identified by a dashed line 310; however, the interlayer dielectric material 110 contains various pores, such as pores 312, 314. The pores 312, 314 are interconnected and provide permeation pathways 316, 318, 320, through which the MLx material may invade the interlayer dielectric material 110 to form the diffusion zone 304. Because MLx tends to decompose under the barrier deposition conditions, the inner surface of the dielectric in the diffusion zone 304 along permeation pathways 316, 318, 320 is coated with conductive or partially conductive material. This coating results in alteration of dielectric properties of interlayer dielectric material 110, with deleterious results affecting device performance and reliability.
While CVD and ALD deposition of conductive barrier materials is desirable for reasons comparatively illustrated in FIGS. 3A and 3B, the use of these processes on porous dielectrics is complicated by the deleterious effects of the permeation zone 304 illustrated in FIG. 3A. These processes alone do not provide a viable solution to preventing permeation.
One proposed solution to this problem is to fill the pores with another dielectric to block the precursor penetration. U.S. Patent Publication No. 2001/0054769, which is incorporated by reference herein, teaches the deposition of a ‘protective layer’ on a dielectric trench. The protective layer blocks pores in the trench, which may be used for dual-damascene wiring applications. For example, a sacrificial protective layer formed of an oxide/nitride/carbide cap is deposited onto a porous dielectric to prevent precursor diffusion by sealing the pores. While this technique largely mitigates the effects of precursor penetration into the dielectric during later deposition steps, depositing the intermediate or sacrificial oxide layer disadvantageously increases the k value of the dielectric, and requires many subsequent processing steps for the removal of the intermediate layer, namely from the via bottom, to maintain low interconnect resistance.